Summary

1And in Conclusion $\dots$ ¶

1.1RISC-V Instructions¶

RISC-V is an assembly language composed of simple instructions that each perform a single task such as addition of two numbers or storing data to memory. Below is a comparison between RISCV code and its equivalent C code:

//x in s0, &y in s1

addi s0, x0, 5  // int x = 5;
sw s0, 0(s1)    // y[0] = x;
mul t0, s0, s0
sw t0, 4(s1)    // y[1] = x * x;

For your reference the tables below show some of the basic arithmetic/bitwise instructions which can also be found on the 61C reference card.

The below are abbreviations that will be used in the table:

rs1: Argument register 1
rs2: Argument register 2
rd: Destination register
imm: Immediate value (integer literal constant)
R[register]: Value contained in register
inst: One of the instructions in the table

Instruction	Name	Description^[2]
`add rd rs1 rs2`	ADD	`R[rd] = R[rs1] + R[rs2]`
`sub rd rs1 rs2`	SUBtract	`R[rd] = R[rs1] - R[rs2]`

Basic Arithmetic Instructions (reprint of Table 1 from this section).

Bitwise Operation	RISC-V: Register	RISC-V: Immediate
AND	`and rd rs1 rs2`	`andi rd rs1 imm`
OR	`or rd rs1 rs2`	`ori rd rs1 imm`
XOR	`xor rd rs1 rs2`	`xori rd rs1 imm`
NOT^[2]	`not rd rs1` (pseudo)
Shift left^[3]	`sll rd rs1 rs2`	`slli rd rs1 imm`
Shift right^[4]	`srl rd rs1 rs2` `sra rd rs1 rs2`	`srli rd rs1 imm` `srai rd rs1 imm`

Basic Bitwise Instructions (reprint of Table 1 from this section).

A RISC-V “immediate” is any numeric constant. For example, addi t0, t0, 20, sw a4, -8(sp), and lw a1, 0x44(t2) have immediates 20, -8, and 0x44 respectively. Note that there is a limit to the size (number of bits) of an immediate in any given instruction (depends on what type of instruction, more on this soon!). You may also see that there is an “i” at the end of certain instructions, such as addi, slli, etc. This means that rs2 becomes an “immediate” or an integer instead of a register. There are immediates in instructions which use an offset such as sw and lw. When coding in RISC-V, always use the 61C reference card for the details of each instruction (the reference card is your friend)!

2Textbook Readings¶

P&H 2.1-2.3

3Additional References¶

See the RISC-V manual links on our RISC-V green card page.

4Exercises¶

Check your knowledge!

4.1Conceptual Review¶

True or False: Types are associated with declaration in C (normally), but are associated with instructions (operators) in RISC-V.

Show Answer

True. See Table 1.

True or False: Since there are only 32 registers, we can’t write RISC-V for C expressions that contain > 32 variables.

Show Answer

False. We have seen a few examples on how to break up longer equations to smaller ones already.

True or False: If p (stored in x9) were a pointer to an array of ints, then p++; would be translated to addi x9,x9, 1.

Solution

False. Don’t forget that ints are 4 bytes wide on RV32I, so instruction would be addi x9, x9, 4.

1And in Conclusion…\dots…¶