Timing a Synchronous System

1Learning Outcomes¶

• Explain why registers help stabilize synchronous systems.

• Compute the delay of a circuit’s critical path.

• Determine the maximum clock frequency for a given circuit.

• Explain a hold time violation and how to avoid it.

Combination logic circuits produce outputs based purely on their input signals. They are used for a wide variety of functions. State elements, on the other hand, have a small number of very specific uses. These are circuits that remember their input signal values.

2Accumulator Example¶

Consider the design of a circuit whose job is to form the sum of a list of integers, $X_0, X_1, X_2, \dots, X_{n-1}$. Assume that some other circuit applies the numbers from the list one at a time—one per clock cycle. Below is a graphical depiction of an abstraction of our circuit used to form the sum–we’ll call the block “sum”. The $X$ values are applied, one per cycle, and after $n$ cycles the sum is present at the output, S.

What should we put inside the sum block to achieve the desired function? Obviously the circuit involves an adder. Also, on each step we need to take the current sum and pass it back to the adder so that it can add another X value to it.

2.1Strawman: Unstable Circuit¶

Figure 2 is our first try:

Let’s examine the operation of this circuit in detail to see if it does the job. Assume that $S$ begins at 0. We then apply $X_0$. After a short delay (the adder propagation delay, $\tau_{add}$) $S$ will change to $X_0$. Then after another $\tau_{add}$ of delay, S will change to $X_0 + X_0$, then after another $\tau_{add}$ of delay, S will change to $X_0 + X_0 + X_0$, etc. Because $\tau_{add}$ is typically less than the clock period, all of these adds of $X_0$ will happen before $X_1$ is applied.

This is clearly not the correct operation of “sum”. The circuit is out of control! We need some way to control the computation, one step at a time.

2.2Use a Register¶

The way to control the computation is to put a register in the feedback path (the connection from the output of the adder to its input), as shown in Figure 3.

The register holds the current value of $S$ while the next one is being formed. After we are happy with the next $S$, we load it into the register and apply the new $X$ value, then wait for a new $S$ to appear at the output of the adder. The process is repeated for all $n$ $X$ values.

Reset signals are a common feature of register circuits. In the circuit diagram, this is the “reset” input signal to the register. This is a signal that can be used to clear the register value, and thus gives us a way to initialize the circuit.

2.3Waveform diagram¶

Figure 4 shows the waveforms demonstrating the rough operation of the accumulator circuit, for a few iterations. Results are generated nicely one at time. In this example, the register is used to hold up the transfer of data from one place to another in the circuit.

The output of the circuit is labeled $S_i$, and the output of the register is labeled $S_{i-1}$ to remind us that the register delays the signal for 1 cycle. So if the output of the circuit is holding the result of the i^th iteration, then the register holds the result of the (i − 1)^th iteration.

2.4Different signal arrival times¶

In practice $X_i$ may not necessarily arrive at the same time as the feedback value, $S_{i−1}$. The waveforms below in Figure 5 show $X$ arriving a little bit later than $S_{i−1}$.

As seen above, on each cycle there is a small time period where the adder has inconsistent inputs. This sort of arrival mismatch and subsequent output instability is common in many circuits. In properly designed circuits, this instability never happens around the rising-edge of the clock and therefore gets ignored by the registers and downstream circuitry.

3Computing Maximum Clock Frequency¶

Notice that the maximum clock frequency (minimum clock period) is limited by the propagation delay of the add/shift operation. If we try to make the clock period too short, then the add/shift logic would not have sufficient time to generate its output and the output register would capture an incorrect value.

At the same time, we seek to create high-bandwidth circuits, which produce many outputs per second. We’d like to find an ideal balance between a high-frequency clock and stable outputs.

Figure 6 shows a typical circuit.

In this circuit, the critical path is:

where clk-to-q delay and setup time are properties of the register (e.g., internal flip flops), and CL delay is the delay through the combinational logic block.

Show Answer

• C. 500 MHz

The critical path is highlighted in Figure 8.

$$\begin{align} \text{critical path} &= \text{clk-to-q delay} + \text{delay of 3 AND gates} + \text{setup time} \\ &= 1 \text{ns} + 3 \text{ns} + 1 \text{ns} \\ &= 5 \text{ns} \end{align}$$

The minimum clock period is 5 ns = 10^-9 seconds per cycle. The maximum frequency is therefore $1/(5 \times 10^{-9} \text{s}) = (0.2 \times 10^9) \text{s}^{-1} = (200 \times 10^6) \text{Hz}$, or 200 MHz.

4Hold Time Violations¶

Above, the critical path determins the maximum clock frequency we can use to ensure a stable input to our register elements. We next present a different problem: hold time violations.

Recall from earlier that the hold time is the duration during which a register’s input d must be stable after the rising edge of the clock. There are some cases where data propagates through the circuit is so fast that the input to registers become unstable during the hold time.

While rare^[1], this may occur if the best-case delay between clocked elements is shorter than the hold time. To mitigate this, we could add arbitrary delay to combinational logic the circuit to increase the best-case delay.